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One execution scenario of AMD IBS: (1) IBS execution control register in CPU is programmed to make the IBS hardware count and sample executed micro-operations. The sampling interval is also written as a field in the control register. The op counter is set to a pseudorandom 7-bit value in the range of 1 to 127. (2) After the profiled thread executes for a while, the value in the op counter equals the sampling interval. As it happens, the next micro-operation will be tagged for sampling. (3) The tagged micro-operation retires. The execution info of the micro-operation is recorded in a number of MSRs. After that, an interrupt is triggered, and the interrupt handler copies the recorded data in the MSRs to a memory buffer in kernel space. (4) Upon copying sampled data, the interrupt handler configures the control register again to re-enable IBS, and the op counter is preloaded with another pseudorandom 7-bit value.

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