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One possible execution scenario of Intel PEBS: (1) Global control register IA32_PERF_GLOBAL_CTRL enables PMC0 and PMC1 by setting its bits corresponding to both counters to one. (2) Global control register IA32_PEBS_ENABLE enables PEBS in PMC0 and PMC1 by setting the bits corresponding to both counters to one. (3) The event select registers IA32_PERFEVTSEL0 and IA32_PERFEVTSEL1 are programmed to make PMC0 and PMC1 count retired loads and retired stores, respectively. (4) The configured PMCs are preloaded with the sampling interval, -N, so that they overflow on elapsing NN events. (5) The profiled program executes for a while; PMC1's counter overflows after N stores occur. PEBS is armed to trap the next store. PMC 1 is preloaded with -N again. (6) Another store occurs after the counter overflow. The armed PEBS hardware traps the access and a microcode records the machine state in a PEBS record in PEBS buffer. (7) If the number of records has reached a specified threshold (1 in this case), an interrupt is triggered, and an interrupt handler transfers the PEBS records to user space.

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