Illustration from Scientific Research

Scheme of the device geometries used: a MGNR (side groups are not shown for clarity) bridges two graphene leads, connected to Au pads. The gate is either an n-doped Si wafer covered with a 300 nm SiO 2 insulating layer (top) or a Pd electrode buried into undoped Si and covered with a 10 nm HfO 2 layer (bottom).

DOI